1. Field of the Invention
The present invention relates to DRAM bit lines, and more particularly, to a method of etching an interlayer dielectric (ILD) that will reduce coupling between adjacent bit lines.
2. Background Information
As DRAMs become more highly integrated, the spacing between individual memory cells decreases. This causes many design and engineering challenges. One of the necessary steps in manufacturing a DRAM is the masking and etching of repetitively patterned interconnects, such as the bit line. The bit line, along with a word line, are the two primary control lines used to read and write to a DRAM memory cell. As the spacing between the typically parallel bit lines decreases, one effect is capacitive coupling between bit lines. One factor that has a large effect on the amount of capacitive coupling is the cross-sectional area of the bit line. For a dual damascene process, the width of the bit line is limited to the critical dimension of the photolithography process. Thus, at the photolithography limit, the cross-section of the bit line cannot be reduced further.
Therefore, what is needed is a method to manufacture bit lines having a reduced cross-section while using photolithography techniques that are currently in use today.